Because handheld and portable electronic systems have increased in complexity, features and performance, designers have focused on low-power design techniques to help reduce the power dissipation of integrated circuits used in these systems.
Low-power design techniques, which can help reduce the power dissipation of integrated circuits used in such systems, are of great importance for handheld devices. Integrated circuits designed specifically for portable devices employ low-power techniques to achieve as low a power dissipation as possible without sacrificing performance.
Typically, I/O pads of integrated circuits dissipate a significant fraction of the total power consumed by the integrated circuit due to large capacitive loads--resulting from the parasitic capacitance of the internal or external I/O pins and pads, I/O pads of external integrated circuits, printed circuit board traces, conductors to external devices coupled to the I/O pads, etc.--that have to be driven from rail to rail (i.e. V.sub.DD to GND). Designers of integrated circuits have little control over either the load capacitance or the voltage swing dictated by the system requirements. Although reducing the load capacitance or the output voltage swing helps to decrease power dissipation, this is rarely an option available to designers of integrated circuits for reducing I/O power dissipation.
Several methods of designing low-power I/O pads employing concepts such as charge sharing (charge recycling) or stepwise charging have appeared in recent literature.
U.S. Pat. No. 5,574,633 discloses a multi-phase charge sharing method and apparatus, wherein existing charge from high voltage output nodes is used to charge lower voltage output nodes so that the lower voltage nodes are partially charged without requiring additional external power. Following the charge transfer, the outputs are disconnected from one another and operated in their normal fashion. U.S. Pat. No. 5,574,633 teaches an energy saving method and apparatus for charge transition in an I/O system of an integrated circuit, wherein the energy savings result from charge sharing. After the energy saving charge sharing the voltage nodes or loads are driven to the operating voltage of the I/O system in order to enable operation.
U.S. Pat. No. 5,638,013 discloses a signal transmission circuit having a plurality of signal lines for supplying potentials to load capacitances, in which each load capacitance is driven by each signal line, and each signal line can be connected to another signal line, the circuit being able to perform a charge redistribution. In this way the total amount of charge and energy consumed for charge transition can be reduced by the charge redistribution. However, this charge redistribution requires a complex circuitry in order to enable the individual connection of each signal line to another signal line. The complex circuitry leads to additional area required on the chip as well as to decreased energy savings due to the energy consumption, i.e. overhead, of this circuitry.
U.S. Pat. No. 5,646,809 discloses a high voltage-tolerant CMOS output driver and high voltage-tolerant input receiver circuit for protection of integrated circuits operating with a lower power supply voltage than externally interfaced devices with a higher power supply voltage. This design solves the problem of adapting an integrated circuit to a mixed 3/5V environment, thereby preventing the integrated circuit from being damaged by external voltages which are higher than the power supply voltage of the integrated circuit. U.S. Pat. No. 5,636,809 does not disclose any method or apparatus for saving energy or reducing the power consumption of an integrated circuit.
U.S. Pat. No. 5,506,535 discloses an I/O circuit that provides bidirectional access to an integrated circuit core which has voltage transformation capability in order to manage different voltage requirements. In order to increase the performance of the integrated circuit core, the size of its features is reduced. In turn, this reduction proportionally reduces the maximum operating voltage of the integrated circuit core. Therefore, the respective I/O circuit suitable for use with the high density integrated circuit core manages to adapt the voltage level of the integrated circuit core to the voltage level being common in the discrete environment of the intergated circuit. The teaching of U.S. Pat. No. 5,506,535 discloses voltage adaptation of integrated-circuit I/O circuits and does not teach an energy saving method or apparatus for performing a charge transition in the I/O circuit of an integrated circuit.
Therefore, according to the state of the art, either no energy saving technology is implemented in the I/O system of integrated circuits or the energy savings result from the benefits conferred by a single energy saving technology and are therefore not sufficient for high frequency integrated circuits operated under low voltage. Moreover, the realization of the above circuits often leads to complex circuits which require much additional logic and additional silicon area on an integrated circuit chip. Further, any complex additional control circuit has a considerable overhead and therefore significantly reduces the amount of energy saved.